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New approach measures strain in semiconductor

MAY 03, 2019
Researchers introduce technique to more efficiently measure strain maps in semiconductor devices.
New approach measures strain in semiconductor internal name

New approach measures strain in semiconductor lead image

Compressive strain in silicon channels enhances the mobility of holes in the semiconductor, and is widely used in semiconductors devices. Previous techniques to measure strain were limited by the small number of sampling points, which hampered processing and data acquisition time for developing strain maps of the semiconductor chips.

Kondo et al. measured the strain in the channels of a tri-gate p-channel metal–oxide semiconductor device, known as a FinFET, using moiré fringes generated by scanning transmission electron microscopy (STEM). The moiré fringes are interference patterns of two gratings produced by an array of sampling points and the crystalline lattice. This novel approach allows the researchers to extract a target lattice of the silicon channel for identifying lattice defects, such as dislocations that significantly affect the strains of the channel.

The team tested this technique on an X–Z slice of a 140-nm-thick sample for measuring its channel strain. The method captures strain information in image acquisition mode, which can be incorporated into standard workflow for configuring the structure of the semiconductor chip. This approach allowed the team to measure strain with an accuracy of 0.1 percent, meeting the needs of the semiconductor industry. They obtained a strain profile of a silicon channel, showing maximum strain of -0.9 percent in less than five minutes.

Yukihito Kondo, an author of the paper, believes this method will contribute to the development of next generation semiconductor devices with more advanced designs, such as having a channel wrapped with gate electrodes as a gate-all-around type field effect transistors.

Source: “Strain measurement of a channel between Si/Ge stressors in a tri-gate field effect transistor utilizing moiré fringes in scanning transmission microscope images,” by Y. Kondo, Y. Aoyama, H. Hashiguchi, C. C. Lin, K. Hsu, N. Endo, K. Asayama, and K-I. Fukunaga, Applied Physics Letters (2019). The article can be accessed at https://doi.org/10.1063/1.5084161 .

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