New MOSFET modeling study raises questions about negative capacitance

A series of recent papers suggest that when a ferroelectric (FE) layer in MOSFETs is arranged in series with the gate stacks, they exhibit room temperature sub-60 millivolt-per-decade (mV/dec) sub-threshold slopes (SS), breaking limitations inherent for silicon-based FETs. A low SS value could enable much lower power computation, which has enormous implications for electronics systems from the internet of things to supercomputers. This tantalizing prospect has resulted in a substantial research effort to understand and commercialize negative capacitance transistors.

Previous work on ferroelectric-based MOSFET with low SS attributed these observations to an S-shaped curve in the free charge versus voltage plot of the FE capacitor. The middle section of such a plot would correspond to a negative capacitance for the transistor. Models based on this assumption assume that the S-curve results from some type of stabilized quasi-static negative capacitance (QSNC) phenomenon. New modeling studies, however, suggest that the apparent negative capacitance is associated with time delays associated with ferroelectric switching.

Their letter shows that FE capacitors cycled under quasi-static conditions always have positive capacitance. The authors also proposed a new model that clarifies conditions for observing a quasi-static apparent negative capacitance in an FE-dielectric stack’s layer. This quantified the requirements of strong interface polarization coupling, in addition to capacitance matching.

Source: “On the validity and applicability of models of negative capacitance and implications for MOS applications,” by J. A. Kittl, B. Obradovic, D. Reddy, T. Rakshit, R. M. Hatcher, and M.S. Rodder, Applied Physics Letters (2018). The article can be accessed at https://doi.org/10.1063/1.5036984 .